System for controlling a change of sequence order of channel data

ABSTRACT

A system for controlling a change of sequence order of channel data for a telecommunication terminal device including: a plurality of channel boards provided to a terminal device and each having transmitting and receiving portions; a multiplexing portion for multiplexing data sent from the channel boards so as to generate transmission data; a demultiplexing portion for demultiplexing reception data so as to send it to the channel boards; and a sequence order address signal generator for generating a sequence order address signal to a memory. The system includes a memory for receiving the sequence order signal and capable of rewriting data for changing a sequence order of channel data; a memory wire control portion for controlling data write access for the memory; and a channel pulse conversion portion for receiving data read out from the memory and for generating a channel pulse corresponding to the data read out from the memory, in which a data communication sequence order between the channel boards and the multiplexing portion is determined by the channel pulse.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a system for controlling a change ofchannel data sequence order for a PCM terminal device and, moreparticularly, to a sequence order control system which allows easydiscrimination of channel data in a PCM terminal device having a numberof channels.

2. Description of the Related Art

A conventional PCM terminal device comprises a plurality of channelboards each having transmitting and receiving portions, a multiplexingportion, a demultiplexing portion, a sequence order signal generator, atransmitting side channel pulse conversion portion, and a receiving sidechannel pulse conversion portion. The multiplexing portion transmits asPCM transmission data a frame constituted of 8-bit time slots TS1, TS2,. . . , TS24 following 1-bit frame identification data. The time slotsTS1, TS2, . . . , TS24 of this data format correspond to transmissiondata sequentially transmitted from a transmitting portion in eachchannel board. In the conventional PCM primary group terminal device,each channel board is connected to a subscriber's telephone, exchange,and other devices.

When the transmitting portion of each channel board receives atransmission pulse from the transmitting side channel pulse conversionportion, it transmits transmission data corresponding to one time slot(8 bits). In this case, the time slots storing channel data of therespective channel boards have a predetermined fixed order, and data istransmitted from the multiplexing portion in this order.

In PCM reception data, the position of each time slot for each channelin the frame is fixed. Therefore, the demultiplexing portion transmitsthe time slot following the 1-bit identification data in thepredetermined order of the channel boards.

The multiplexing portion multiplexes data transmitted from the channelboards as PCM transmission data in the predetermined order. Thus, thetransmitting side channel pulse converter transmits the channel pulse P1to the corresponding channel board transmitting portion to cause it togenerate 8-bit transmission data, and then transmits the channel pulseP2 to the corresponding transmitting portion to cause it to generate8-bit transmission data. In this way, when channel pulses P1, P2, . . ., P24 are sequentially transmitted to the transmitting portions of thechannel boards, 8-bit transmission data is sequentially supplied to themultiplexing portion. Thus, the multiplexing portion generates the frameconsisting of the time slots following the 1-bit identification bit.This control is repeated, and PCM transmission data is transmitted.

The demultiplexing portion processes PCM reception data in a manneropposite to that of the PCM transmission data. Since the order of timeslots including the channel data in the frame is fixed, the channelpulses P1, P2, . . . are transmitted to the channel boards correspondingto the above order, and each time slot can be distributed to thereceiving portion of the corresponding channel board.

The sequence order signal generator generates an order signal forgenerating the pulses P1, P2, . . . at predetermined time intervals inresponse to instructions from the multiplexing and demultiplexingportions. Upon reception of the order signal, the transmitting andreceiving side channel pulse conversion portions sequentially transmitthe channel pulses.

There is a strong demand for modifying the PCM terminal device bysoftware without modifying the hardware when an office is moved.However, in the conventional PCM terminal device, since the order ofchannel data and time slots in the frame is predetermined, it isdifficult to respond to this demand.

Furthermore, there is a demand for monitoring the operating state ofeach channel board by checking a specific time slot. However, only anoutput signal of a specific channel is present in the specific timeslot. For example, when time slots are used for monitoring the operatingstate, since each time slot includes only the output from a certainchannel board, the output state of other channel boards cannot bechecked. Hence, when monitoring operation is performed using a specifictime slot, the outputs of other channel boards must be allocated in thetime slot. When this time slot is at a first position, an output of achannel board is inserted therein, and when at a second position, anoutput of another channel board is to be inserted. In this way, data ofthe channel boards must be exchanged. However, such an operation iscomplex, resulting in inconvenience.

Therefore, the present invention intends to solve the above drawbackswith a simple method.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a system forcontrolling a change of channel data sequence order for a PCM terminaldevice which can easily discriminate channel data sequence order bychanging data written in a memory without modifying the hardware.

It is another object of the present invention to provide a channel datasequence order control system which can replace data between differentDI groups by changing data written in a memory without modifying thehardware.

According to a basic aspect of the present invention, there is provideda system for controlling a change of channel data sequence order for atelecommunication terminal device including: a plurality of channelboards provided to a terminal device and each having transmitting andreceiving portions; a multiplexing portion for multiplexing data sentfrom the channel boards so as to generate transmission data; ademultiplexing portion for demultiplexing reception data so as to sendit to the channel boards; and a sequence order address signal generatorfor generating a sequence order address signal to a memory. The systemincludes a memory for receiving the sequence order address signal andcapable of rewriting data for changing a sequence order of channel data;a memory write control portion for controlling data write access for thememory; and a channel pulse conversion portion for receiving data readout from the memory and for generating a channel pulse corresponding tothe data read out from the memory, wherein a data communication sequenceorder between the channel boards and the multiplexing portion isdetermined by the channel pulse.

According to another aspect of the present invention, there is provideda system for controlling a change of sequence order of channel data fora telecommunication terminal device including: a plurality of groups ofchannel boards, each of said groups consisting of a plurality of channelboards, each of said channel boards having a transmitting portion and areceiving portion; a first channel data sequence order selector portionfor receiving data sent from the channel board group; a second channeldata sequence order selector portion for demultiplexing reception dataso as to supply it to the channel board group; and a sequence orderaddress signal generator for generating a sequence order address signalto a memory. The system includes a memory for receiving the sequenceorder address signal and capable of rewriting data for changing asequence order of channel data; a memory write control portion forcontrolling data write access for the memory; and a channel datasequence order selector control portion for receiving data read out fromthe memory and for supplying a control signal to the channel datasequence order selector portion, wherein a data communication sequenceorder between the channel board groups and the first and second channeldata sequence order selector portions is determined based on the dataread out from the memory.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1, 1A and 1B are block diagrams explaining a conventional device;

FIGS. 2, 2A and 2B are block diagrams showing a channel data sequence orcontrol system according to an embodiment of the present invention;

FIGS. 3 and 4 are diagrams explaining the relationship between timeslots and channel data;

FIG. 5 is a diagram explaining a method for deriving 5-bit address datafrom a memory;

FIG. 6 is a diagram explaining original data stored at correspondingaddresses of a memory;

FIG. 7 is a diagram explaining a case when a channel 1 is replaced witha channel 2;

FIGS. 8, 8A and 8B are block diagrams showing a DI group shown in FIG. 2in more detail; and

FIG. 9 is a table explaining the relationship between control data and aselector operating state.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Prior to a description of an embodiment of the present invention, aconventional PCM terminal device will be described with reference toFIG. 1.

A conventional PCM terminal device shown in FIG. 1 comprises channelboards 101, 102, . . . , 124 each having transmitting and receivingportions, a multiplexing portion 11, a demultiplexing portion 15,sequence order signal generators 12 and 16, a transmitting side channelpulse conversion portion 14, a receiving side channel pulse conversionportion 18, and the like. The multiplexing portion 11 transmits a frameconsisting of 8-bit time slots TS1, TS2, . . . , TS24 following 1-bitframe identification data. The time slots TS1, TS2, . . . , TS24 of adata format correspond to transmission data sequentially transmittedfrom the transmitting portions of the channel boards 101, 102, . . . ,124. The channel boards 101, 102, . . . , 124 are connected to asubscriber's telephone, an exchange, and other devices.

When the transmitting portions of the channel boards 101, 102, . . . ,124 receive transmission pulses P1, P2, . . . , P24 from thetransmitting side channel pulse conversion portion 14, they transmittransmission data corresponding to one time slot (8 bits). The timeslots TS1, TS2, . . . , TS24 storing the channel data of the channelboards 101, 102, . . . , 124 have a predetermined order, and themultiplexing portion 11 transmits data in this order.

PCM reception data also has predetermined time slot positions in theframe. Hence, the demultiplexing portion 15 transmits the time slotsfollowing the 1-bit identification data to the corresponding receivingportions in the order of the channel boards 101, 102, . . . , 124.

In order to multiplex data sent from the channel boards 101, 102, . . ., 124 as PCM transmission data in the predetermined order, the portion14 transmits the channel pulse P1 to the channel board 101 to cause itto generate 8-bit transmission data, and then transmits the channelpulse P2 to the channel board 102 to cause it to generate another 8-bittransmission data. In this way, when the channel pulses P1, P2, . . . ,P24 are sequentially transmitted to the corresponding transmittingportions of the channel boards 101, 102, . . . , 124, the 8-bittransmission data can be sequentially transmitted to the multiplexingportion 11. Thus, the portion 11 can generate the frame consisting ofthe time slots TS1, TS2, . . . , TS24 following the 1-bit identificationdata. This control is repeated, and the PCM transmission data istransmitted.

The demultiplexing portion 15 processes PCM reception data in a manneropposite to that of the PCM transmission data. Since the order of timeslots including the channel data in the frame is fixed, the channelpulses P1, P2, . . . are transmitted to the channel boards correspondingto the above order, and each time slot can be distributed to thereceiving portion of the corresponding channel board.

The sequence order signal generators 12 and 16 generate an order signalfor generating the pulses P1, P2, . . . at predetermined time intervalsin response to instructions from the multiplexing and demultiplexingportions. Upon reception of the order signal, the transmitting andreceiving side channel pulse conversion portions sequentially transmitthe channel pulses.

A channel data sequence order control system according to an embodimentof the present invention will be described with reference to FIG. 2.

Referring to FIG. 2, reference numeral 11 denotes a multiplexingportion; 12, a sequence order address generator; 13, a transmitting sidememory portion; 14, a transmitting side channel pulse conversionportion; 15, a demultiplexing portion; 16, a sequence order signalgenerator; 17, a receiving side memory portion; 18, a receiving sidechannel pulse conversion portion; 19, a write control portion; and 101to 124, channel boards each having transmitting and receiving portions.

The multiplexing portion 11 multiplexes data transmitted from thechannel boards (CH1 to CH24) 101, 102, . . . , 124 as PCM transmissiondata.

The sequence order address generator 12 sequentially generates addresses(e.g., 5-bit address data, as shown in FIG. 5) for accessing the memoryportion 13 in accordance with the time slots. Therefore, the generator12 generates addresses "00001", "00010", "00011", . . . .

The memory portion 13 stores channel pulse generation data whichindicates to which channel boards (CH1 to CH24) 101, 102, . . . , 124the channel pulse is to be selectively generated. For example, theportion 13 comprises rewritable memories, e.g., a PROM, an E² ROM, aRAM, and the like. The output data from the portion 13 has a 5-bitconfiguration. For example, when the address data sequentially changes"1", "2", "3", . . . in the decimal notation as shown in FIG. 5, data"1", "2", "3", . . . in the decimal notation is generated in response.

The transmitting side channel pulse conversion portion 14 generateschannel pulses for instructing supply of transmission data to thechannel boards (CH1 to CH24) 101, 102, . . . , 124 in response to thechannel pulse generation data sent from the memory portion 13. Forexample, when data "1" in the decimal notation is supplied, the portion14 transmits the channel pulse P1 only to the channel board (CH1) 101.Upon reception of data "2" in the decimal notation, the portion 14transmits the channel pulse P2 only to the channel board (CH2) 102.Therefore, when the channel pulse generation data "1", "2", "3", . . .in the decimal notation is generated from the memory portion 13, theportion 14 sequentially generates the channel pulses P1, P2, P3, . . .in response.

When the demultiplexing portion 15 receives the multiplexed PCM signal,it operates to accurately control the distribution of the time slots tothe corresponding channel boards.

The sequence order address generator 16 sequentially generates addressdata for accessing the memory portion 17 in accordance with the timeslots, and is operated in the same manner as the generator 12.

The memory portion 17 stores channel pulse generation data whichindicates to which channel boards (CH1 to CH24) 101, 102, . . . , 124the channel pulse is to be selectively supplied. The portion 17 has thesame arrangement as that of portion 13.

The receiving side channel pulse conversion portion 18 selectivelygenerates the channel pulses for instructing reception of data to thechannel boards (CH1 to CH24) 101, 102, . . . , 124 in accordance withthe channel pulse generation data from the memory portion 17, and isoperated in the same manner as the portion 14.

The write control portion 19 performs various control operations forwriting data in the memory portion 13 or 17, and can change the channelpulse generation data generated from the memory portion 13 with respectto an identical address.

The operation of the system shown in FIG. 2 will be described.

The operation in a normal state will first be described. The writecontrol portion 22 writes the channel pulse generation data in thememory portion 13 so that decimal data "1", "2", "3", . . . , "24" isgenerated in correspondence with address data 1, 2, 3, . . . , 24, asshown in FIG. 6. The address data 1, 2, . . . is then sequentiallygenerated by the generator 12. Thus, the channel pulse generation datais sequentially supplied to the conversion portion 14. In response tothis, the portion 14 first supplies the channel pulse P1 to thetransmitting portion of the channel board (CH1) 101, and then suppliesthe channel pulse P2 to the transmitting portion of the channel board(CH2) 102. In this manner, based on the channel pulse generation data"1", "2", . . . , the channel pulses P1, P2, . . . are sequentiallytransmitted to the channel boards (CH1, CH2, . . . ) 101, 102, . . . ,124. (See FIG. 3) Upon reception of the pulses, the transmittingportions of the channel boards (CH1, CH2, . . . ) 101, 102, . . . , 124individually supply 8-bit data to the multiplexing portion 11, whichmultiplexes the reception data. Thus, as shown in FIG. 6, the frame inwhich the data from the channel boards (CH1, CH2, . . . ) 101, 102, . .. , 124 is distributed to the time slots TS1, TS2, . . . is formed, andis generated as the PCM transmission data.

Unless the write control portion 19 changes the storage data of thememory portion 13, the frame data having this data distribution order istransmitted. In this case, since the receiving side can identify thedistribution order of the frame data, the same data as that in thememory portion 13 is stored in the memory portion 17. Therefore, whenthe address data 1, 2, . . . , is generated from the sequence orderaddress generator 16, the channel pulse generation data "1", "2", . . .is generated from the memory portion 17. Upon reception of the data "1","2", . . . , the conversion portion 18 sequentially transmits thechannel pulses P1, P2, . . . to the receiving portions of the channelboards (CH1, CH2, . . . ) 101, 102, . . . , 124. In this way, the datain the corresponding time slots TS1, TS2, . . . is received by thepredetermined channel boards (CH1, CH2, . . . ) 101, 102, . . . , 124.

The operation for changing the channel data sequence order will now bedescribed.

A case will be described wherein the output from the channel board (CH1)is arranged in the time slot TS2, and the output from the channel board(CH2) is arranged in the time slot TS1. The write control portion 19writes data in the memory portion 13. In this case, the data at theaddress 1 is stored at the address 2. (see FIG. 7) When the address datanormally 1, 2, . . . , 24 is generated from the generator 12, thechannel pulses P1, P2, . . . are transmitted from the conversion portion14 to the channel boards (CH1, CH2, . . . ) 101, 102, . . . , 124.

However, since decimal data "1" is written at the address 2, the channelpulse is transmitted to the channel board (CH1) 101. Hence, themultiplexing portion 11 generates first frame data in which datagenerated from the channel board (CH1) 101 is stored in the time slotTS2. (see FIG. 4)

At the receiving side, the write control portion 19 controls the memoryportion 17 so as to distribute the reception data to the predeterminedchannel boards in the same manner as the memory portion 13. Thus, datareceived in other channel boards can be sequentially distributed to aspecific channel board at the reception side.

As described above, the output from the channel board (CH1) can bearranged in the time slot TS2, and the output from the channel board(CH2) can be arranged in the time slot TS1. It should be noted that theabove-mentioned address data and output data from the memory portionshave a 5-bit configuration.

FIG. 8 shows a modified embodiment of the present invention that isapplied to a PCM primary group terminal device.

Referring to FIG. 8, reference numeral 31 denotes a transmitting sidesequence order selector, which performs sequence order control of datain identical time slots transmitted from DI groups (DG1 to DG4) 1001 to1004 based on a control signal (to be described later); 14, atransmitting side sequence order selector control portion, whichgenerates a control signal for controlling the selector 31 based oncontrol data supplied from a memory portion 13; and 13, a memory portionstoring control data for controlling the selector 31.

Reference numeral 12 denotes a sequence order address generator, whichsequentially generates address data for accessing the memory portion 13;11, a sync multiplexing portion for performing various controloperations (e.g., for generating a reference signal for transmissiontimings of multiplexing); 32, a receiving side sequence order selector,which performs sequence order control of a reception signal with respectto any of the DI groups (DG1 to DG4) 1001 to 1004; 18, a receiving sidesequence order selector control portion, which generates a controlsignal for controlling the selector 32 based on control data suppliedfrom a memory portion 17; 16, a sequence order address generator, whichsequentially generates address data for accessing the memory portion 17;15, a sync demultiplexing portion for performing various controloperations (e.g., for establishing frame synchronization by multiplexeddata so as to generate a reference signal for a reception timing); and22, a write control portion which performs various control operationsfor writing control data into the memory portion 13 or 17, and canchange the control data generated at the identical address. In addition,reference numeral 21 denotes a data selector means.

The memory portion 13 will now be described. The memory portion 13stores control data which is decoded by the control portion 14 andgenerates switching data for switching control of the selector 31. Forexample, as shown in FIG. 9, when the control data corresponds todecimal number "1", the control portion 14 generates switching data forconnecting an input line L1 to an output line l1; L2 to l2; L3 to l3;and L4 to l4. On the other hand, when the control data corresponds todecimal number 2, the control portion 14 generates the switching datafor connecting L1 to l1: L2 to l3; L3 to l2; and L4 to l4. That is, thelines L2 and L3 are swapped. When the control data corresponds todecimal number "3", the control portion 14 generates the switching datafor connecting the line L1 to the line l1; L2 to l2; L3 to l4; and L4 tol3. That is, the lines L3 and L4 are replaced. When the control datacorresponds to decimal number "15", the portion 14 generates theswitching data for connecting the line L1 to the line l3; L2 to l1; L3to l4; and L4 to l3. Since the memory portion 13 is accessed based on,e.g., 5-bit address data, it can store 32 control data. The selectoroperation based on the control data 4 to 14, 16, . . . (not shown inFIG. 9) can be freely set, and a further description thereof will beomitted. Therefore, predetermined sequence order control is achievedsuch that necessary data from the memory portion 13 is selectivelywritten in the write control portion 22 in accordance with individualsequence order control conditions.

At the receiving side, the operation opposite to above can be performed.For example, when the control data from the memory portion 17corresponds to decimal number "1", the control portion 18 generates theswitching data for connecting an input line l1' of the selector 32 to anoutput line L1'; l2' to L2'; l3' to L3'; and l4' to L4'. When thecontrol data corresponds to decimal number "2", the control portion 18generates the switching data for connecting the line 1' to the Line L1';l2' to L340 ; l3' to L2'; and l4' to L4'. When the control datacorresponds to decimal number "3", the portion 18 generates theswitching data for connecting the line l1' to the line L1'; l2' to L2';l3' to L4'; and l4' to L3'. The sequence order to be changed differs inaccordance with applications, and the control data corresponding to eachapplication is selectively written under the control of the writecontrol portion 22.

The operation of the system shown in FIG. 8 will be described.

The normal operation will now be described. In this case, datacorresponding to decimal number "1" is prestored at all the addresses ofthe memory portion 13. Therefore, even if the generator 12 generates theaddress data "1", "2", . . . , "24", the control data "1" is read outfrom the memory portion 13. As a result the connection between lines L1to l1, L2 to l2, L3 to l3, and L4 to l4 are maintained based on theswitching data generated from the control portion 14. Thus, data whichis not subjected to sequence order control among data strings fromrespective channels, i.e., a plurality of sets of synchronized serialdata, are generated.

The operation for channel data sequence order control will be described.In this case, decimal data "1", "2", . . . , "15" are prestored at theaddresses 1, 2, . . . , 24 of the memory portion 13, respectively.Therefore, when the generator 12 sequentially generates the address data"1", "2", . . . , "24", the control data "1", "2", . . . ,"15"corresponding thereto is sequentially read out from the portion 13.When the control data "1" is supplied, connection between the lines L1to l1, L2 to l2, L3 to l3, and L4 to l4 is performed. However, when thecontrol data is "2", connection between lines L1 to l1, L2 to l3, L3 tol2, and L4 to l4 is performed, and a sequence order of 1-word data onthe lines L2 and L3 is changed. When the control data is "15",connection between lines L1 to l3, L2 to l1, L3 to l4, and L4 to l2 isperformed, and the sequence order of each channel data string ischanged. This sequence order control state is an example. When therelationship between the control data and the switching data isdetermined in advance and the control data is written in the memoryportion 13 under the control of the write control portion 22, thechannel data sequence order control for each time slot or each frame canbe performed desirably.

In the above embodiment, the data sequence order control among channeldata strings has been described. A multiplexing order in the channeldata string can be changed by modifying the DI groups. A generationorder of the transmitting side channel pulses from a sequence orderaddress generator is controlled by data written in a memory portion.However, when data corresponding to decimal number "2" is generated fromthe memory portion, if the transmitting side channel pulse conversionportion generates the channel pulses in the order of P1, P3, P2, P4, . .. , P24, transmission data can be multiplexed in the order of channelboards CH1, CH3, CH2, . . . , CH24. In this way, a plurality of channelpulse generation conditions between data from the memory portion and thetransmitting side pulse conversion portion are determined in advance,and data is selectively written in the memory portion by the writecontrol portion, thus changing the channel data order.

Therefore, when control circuits are respectively provided for the DIgroups (DG 1 to DG4) 1001 to 1104, word positions not only among channeldata strings but also in each channel data string can be controlled.

In the above descriptions, the DI groups comprise 24 channel boards, andthe output data or address data from the memory portion has a 5-bitconfiguration. However, the present invention is not limited to thosearrangements, and other bit numbers can be selected.

We claim:
 1. A system for controlling a change of sequence order ofchannel data for a telecommunication terminal device, comprising:aplurality of channel boards provided to a terminal device and eachhaving transmitting and receiving portions; a multiplexing portion,connected to said channel boards, for multiplexing data sent from saidchannel boards so as to generate transmission data; a demultiplexingportion, connected to said channel boards, for demultiplexing receptiondata so as to send it to said channel boards; a first sequence orderaddress signal generator, connected to said multiplexing portion, forgenerating a multiplex sequence order address signal; a second sequenceorder address signal generator, connected to said demultiplexingportion, for generating a demultiplex sequence order address signal; atransmitting memory, connected for said first sequence order addressgenerator, for receiving the multiplex sequence order address signal andproducing transmitting pulse sequence data, and capable of rewritingdata for changing a multiplex sequence order of the channel data; areceiving memory, connected to said second sequence order addressgenerator, for receiving the demultiplex sequence order address signaland producing receiving pulse sequence data, and capable of rewritingdata for changing a demultiplex order of the channel data; a memorywrite control portion for controlling data write access for thetransmitting and receiving memories; a receiving channel pulseconversion portion, connected to said receiving memory and said channelboards, for receiving the receiving pulse sequence data from saidreceiving memory and for generating a receiving channel pulse,corresponding to the data read out from said receiving memory,activating one said channel boards; and a transmitting channel pulseconversion portion, connected to said transmitting memory and saidchannel boards, for receiving the transmitting pulse sequence data readout from said transmitting memory and generating a transmitting channelpulse, corresponding to the data read out from said transmitting memory,activating one of said channel boards, data communication sequence orderbetween said channel boards and said multiplexing and demultiplexingportions being determined by the transmitting and receiving channelpulses.
 2. A system for controlling a change of sequence order ofchannel data for a telecommunication terminal device, comprising:aplurality of groups of channel boards, each of said channel boardshaving a transmitting portion and a receiving portion; a first channeldata sequence order selector portion, connected to said channel groups,for receiving data sent from said channel board group; a second channeldata sequence order selector portion, connected to said channel groups,for demultiplexing reception data so as to supply it to said channelboard group; a first sequence order address signal generator forgenerating a transmitting sequence order address signal; a secondsequence order address signal generator for generating a receivingsequence order address signals; a transmitting memory, connected to saidfirst sequence order address signal generator, for receiving thetransmitting sequence order address signal and producing transmittingsequence order data, and being rewritten for changing a transmittingsequence order of channel data; a receiving memory, conencted to saidsecond sequence order address signal generator, for receiving thereceiving sequence order address signal and producing receiving sequenceorder data, and being rewritten for changing a receiving signal order ofchannel data; a memory write control portion for controlling data writeaccess for said transmitting and receiving memories; a transmittingchannel data sequence order selector control portion, connected to saidtransmitting memory and said first channel data sequence order selectorportion, for receiving the transmitting sequence order data read outfrom said memory and supplying a control signal to said first channeldata sequence order selector portion activating one of said groups; anda receiving channel data sequence order selector control portion,connected to said receiving memory and said second channel data sequenceorder selector portion, for receiving receiving sequence order data readout from said memory and supplying a control signal to said secondchannel data sequence selector portion activating one of the groups,data communication sequence order between said channel board groups andsaid first and second channel data sequence order selector portionsbeing determined based on the sequence order data read out from saidmemory.